Formal Verification of Timed VHDL Programs
نویسندگان
چکیده
The verification of timed digital circuits is an important issue. These circuits are composed by logical gates, each of them being associated with propagation delays. The analysis of such circuits is necessary to identify critical path and adjust the clock period of the circuit or to determine the stability period of input/ouput signals. These circuits are represented by a functional model described in VHDL and a timing model associating propagation delays to each functional block. This model is translated into timed automata formalism upon which classical simulation or model checking verification can be performed. This method rises two problems: 1) Propagation delays associated to a gate depend on the transistor assembly and the manufacturer’s technology. How do we associate propagation delays to a logical gate ? 2) How to automatically translate a VHDL functional description, combined with propagation delays, into timed automata ? This paper addresses these two problems. It presents a method automating the verification of VHDL descriptions, augmented with interval bounded propagation delays, obtained by electrical simulation of the transistor model of the gates.
منابع مشابه
An Automatic Design Flow from Formal Models to FPGA
SMV [McM93] is a language suitable for integrated circuit design and optimized for formal verification. VHDL [IEE93] is a design format suitable for simulation and synthesis, but poorly designed for formal verification purposes. The contribution of this paper is the integration of the two approaches through the definition of systematic rules to translate SMV programs into VHDL descriptions, pro...
متن کاملControl Interpreted Petri Nets – Model Checking and Synthesis
The chapter presents a novel approach to formal verification of logic controller programs [2], focusing especially on reconfigurable logic controllers (RLCs). Control Interpreted Petri Nets [8] are used as formal specification of logic controller behavior. The approach proposes to use an abstract rule-based logical model presented at RTL-level. A Control Interpreted Petri Net is written as a lo...
متن کاملRTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
This paper describes a tool-supported methodology for the register-transfer-level formal verification of a growing hardware design paradigm--timed asynchronous systems. These systems are a network of communicating asynchronous and synchronous components and have correctness constraints that depend on specified bounded delays. This paper formalizes the verification problem and demonstrates how t...
متن کاملTransforming VHDL to Timed Automata
This report presents the transformation of behavioral VHDL programs to Timed Automata.
متن کاملFormal Modeling of Timed Function Blocks for the Automatic Verification of Ladder Diagram Programs
We describe our approach to the automated verification of Ladder Diagrams programs. This combines a formal semantics for a large fragment of the LD language (including a modeling of timed function blocks), and a powerful temporal logic model checking technology.
متن کامل